Low-power cordic multiplier design using approximate arithmetic for energy-efficient computing
Email:
anhnd@utc.edu.vn
Từ khóa:
Approximate computing, CORDIC, low-power, multiplier, Gaussian filter, edge detection
Tóm tắt
In digital IC design, low-power CORDIC-based multipliers have attracted significant attention due to their potential to integrate approximate adders for reducing energy and area costs. While CORDIC is hardware-efficient, its precise design still has room for improvement, particularly in terms of power consumption and area overhead. To address this, we present an approach to enhance the CORDIC multiplier using Approx. Adders from the EvoApproxLib library. The proposed design offers multiple variants with different optimization targets: up to 19.3% power reduction in CORDIC + Approx. Adder, 11.5% area savings in CORDIC + Approx. Adder, and 14.7% frequency improvement in CORDIC + Approx. Adder compared to the conventional exact CORDIC multiplier. When applied to Gaussian filtering and Sobel edge detection, optimal variants such as CORDIC + Approx. Adder and CORDIC + Approx. Adder yield PSNR values of 60 and 48 dB respectively, with SSIM values exceeding 0.990, indicating minimal quality loss. The evaluation shows that 8–10 iterations provide the best efficiency-accuracy trade-off, enabling designers to select appropriate variants based on specific application requirements. These results demonstrate the effectiveness of the proposed method for energy-constrained, error-tolerant systems in IoT devices, edge computing, and image processing applicationsTài liệu tham khảo
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[2]. C. Guo, F. Luo, Z. Cai, Z.Y. Dong, Integrated energy systems of data centers and smart grids: State-of-the-art and future opportunities, Applied Energy, 301 (2021) 117474. https://doi.org/10.1016/j.apenergy.2021.117474
[3]. A. Changela, M. Zaveri, D. Verma, A comparative study on CORDIC algorithms and applications, Journal of Circuits, Systems and Computers, 32 (2023) 2330002. https://doi.org/10.1142/S0218126623300027
[4]. F. Lyu, C. Wu, Y. Wang, H. Pan, Y. Wang, Y. Luo, An optimized hardware implementation of the CORDIC algorithm, IEICE Electronics Express, 19 (2022) 20220362. https://doi.org/10.1587/elex.19.20220362
[5]. N. Bai, R. Qu, Y. Xu, Y. Wang, X. Chen, L. Li, Low-iteration hybrid computing CORDIC architecture, Microelectronics Journal, 156 (2025) 106481. https://doi.org/10.1016/j.mejo.2024.106481
[6]. J. Deng, J. Yang, X. Wang, An Efficient FP16-Based Hardware Architecture with Enhanced CORDIC to Implement Sigmoid and Tanh Functions, 2024 IEEE 7th Information Technology, Networking, Electronic and Automation Control Conference, 7 (2024). https://doi.org/10.1109/ITNEC60942.2024.10733095
[7]. K. Li, H. Fang, Z. Ma, F. Yu, B. Zhang, Q. Xing, A Low-latency CORDIC algorithm based on pre-rotation and its application on computation of arctangent function, Electronics, 13 (2024) 2338. https://doi.org/10.3390/electronics13122338
[8]. Y. Wu, C. Chen, W. Xiao, X. Wang, C. Wen, J. Han, X. Yin, W. Qian, C. Zhuo, A survey on approximate multiplier designs for energy efficiency: From algorithms to circuits, ACM Transactions on Design Automation of Electronic Systems, 29 (2024) 1-37. https://doi.org/10.1145/3610291
[9]. R. Kobayashi, I. Okubo, K.N. Dang, ApproxiMorph: energy-efficient neuromorphic system with layer-wise approximation of spiking neural networks and 3D-stacked SRAM, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (2025). https://doi.org/10.1109/TCAD.2025.3597251
[10]. V. Mishra, S. Mittal, S. Singh, D. Pandey, R. Singhal, Mega-mac: a merged accumulation based approximate mac unit for error resilient applications, Proceedings of the Great Lakes Symposium on VLSI, (2022) 1-4. https://doi.org/10.1145/3526241.3530384
[11]. A.M. Dalloo, D.A. Abdulhussein, M.M. Sabry, A.J. Humaidi, A.R.J. Almusawi, R. Woods, N. TaheriNejad, Approximate computing: Concepts, architectures, challenges, applications, and future directions, IEEE Access, (2024). https://doi.org/10.1109/ACCESS.2024.3467375
[12]. R. Kobayashi, K.N. Dang, An efficient hardware implementation of spiking neural network using approximate Izhikevich neuron, 9th International Conference on Integrated Circuits, Design, and Verification, (2024). https://doi.org/10.1109/ICDV61346.2024.10616602
[13]. G. Narmadha, S. Kanniyappan, V. Dhilip Kumar, P. Ramu, A low power and high speed Approx. Adder for image processing applications, Journal of Engineering Research, 10 (2022) 150-160. https://doi.org/10.36909/jer.10037
[14]. B. Khurshid, High-performance CORDIC-based approximate MAC architectures for FPGA platforms, Integration, 101 (2025) 102338. https://doi.org/10.1016/j.vlsi.2024.102338
[15]. Chung R.L., Hsueh Y., Chen S.L., Abu P.A.R., Efficient and accurate cordic pipelined architecture chip design based on binomial approximation for biped robot, Electronics, 11(11) (2022) 1701. https://doi.org/10.3390/electronics11111701
[16]. H. Chen, K. Cheng, Z. Lu, Y. Fu, L. Li, Low-complexity high-precision method and architecture for computing the logarithm of complex numbers, IEEE Transactions on Circuits and Systems I: Regular Papers, 68 (2021) 3293-3304. https://doi.org/10.1109/TCSI.2021.3081517
[17]. H.H. Que, H.Y. Lin, X. Yin, C. Zhuo, J. Han, A Survey of approximate computing: from arithmetic units design to high-level applications, Journal of Computer Science and Technology, 38 (2023) 251-272. https://doi.org/10.1007/s11390-023-2537-y
[18]. M.A. Hanif, R. Hafiz, M. Shafique, DAEM: A data-and application-aware error analysis methodology for Approx. Adders, Information, 14 (2023) 570. https://doi.org/10.3390/info14100570
[19]. P. Balasubramanian, R. Nayar, D.L. Maskell, Gate-level static Approx. Adders: a comparative analysis, Electronics, 10 (2021) 2917. https://doi.org/10.3390/electronics10232917
[20]. V. Lakshmi, V. Pudi, J. Reuben, In-memory implementation of an Approx. Adder with reduced latency and error, IEEE Transactions on Circuits and Systems I: Regular Papers, (2024). https://doi.org/10.1109/TCSI.2024.3511955
[21]. E. Farahmand, M.E. Salehi, S. Mohammadi, A. Yazdanbakhsh, Design and analysis of high performance heterogeneous block-based Approx. Adders, ACM Transactions on Embedded Computing Systems, 22 (2023) 1-32. https://doi.org/10.1145/3625686
[22]. M.Češka, J. Matyáš, V. Mrazek, L. Sekanina, Z.Vasicek, T.Vojnar, Designing approximate arithmetic circuits with combined error constraints, 25th Euromicro Conference on Digital System Design, (2022). https://doi.org/10.1109/DSD57027.2022.00110
[23]. B. Khurshid, J.J. Khan, An efficient fixed-point multiplier based on CORDIC algorithm, Journal of Circuits, Systems and Computers, 30 (2021) 2150080. https://doi.org/10.1142/S0218126621500808
[24]. H. Nair, A. Chalil, FPGA implementation of area and speed efficient CORDIC algorithm, 6th International Conference on Computing Methodologies and Communication, (2022). https://doi.org/10.1109/ICCMC53470.2022.9753730
Tải xuống
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Nhận bài
08/09/2025
Nhận bài sửa
02/10/2025
Chấp nhận đăng
07/10/2025
Xuất bản
15/01/2026
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Kiểu trích dẫn
Thanh Dat, N., Van Vu, L., Quang Thai, P., Duy Anh, N., Khanh N., D., Nguyen Khanh, L., & Dao Thanh, T. (1768410000). Low-power cordic multiplier design using approximate arithmetic for energy-efficient computing. Tạp Chí Khoa Học Giao Thông Vận Tải, 77(1), 30-42. https://doi.org/10.47869/tcsj.77.1.3
