Timing bottleneck characterization in an iterative Keccak-f[1600]/SHA3-256 core: An FPGA/ASIC study
Email:
thanhngoc@actvn.edu.vn
Từ khóa:
Keccak, SHA-3, FPGA, ASIC, timing closure, standard-cell library
Tóm tắt
The Keccak-f[1600] permutation underlies the Secure Hash Algorithm 3 (SHA-3) family of cryptographic hash functions, widely used for data integrity and, increasingly, in post-quantum cryptographic hardware. Iterative implementations reuse one round datapath for all 24 rounds through a wide feedback multiplexer, a resource-efficient choice whose timing has not previously been measured with post-route accuracy. This study analyzes an iterative SHA3-256 core implemented on a Xilinx Artix-7 field-programmable gate array (FPGA) and cross-checked on a Virtex-7 device, comparing post-synthesis and post-route timing and evaluating two fan-out-reduction techniques and a multicycle-path exception. The same design was also taken through a complete register-transfer level (RTL) to GDSII flow on a 45 nm process as an application-specific integrated circuit (ASIC), using an in-house-characterized standard-cell library and a widely used public library, with functional correctness verified against reference test vectors. Post-synthesis estimates underestimate the critical-path delay of the feedback-select path by up to 2.8×, none of the three mitigation techniques improves the operating frequency, and the bottleneck is architecture-induced rather than technology-dependent. The in-house library achieved a signed-off implementation with zero design-rule check (DRC) and layout-versus-schematic (LVS) violations, whereas cell-level verification found manufacturing-grid violations in the public library that prevented a comparable signoff.Tài liệu tham khảo
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[2]. G. Bertoni, J. Daemen, M. Peeters, G. Van Assche, The Keccak reference, Keccak Team (2011).
[3]. National Institute of Standards and Technology, Module-Lattice-Based Digital Signature Standard, FIPS PUB 204 (2024).
[4]. National Institute of Standards and Technology, Module-Lattice-Based Key-Encapsulation Mechanism Standard, FIPS PUB 203 (2024).
[5]. R. Avanzi, J. Bos, L. Ducas, E. Kiltz, T. Lepoint, V. Lyubashevsky, J. M. Schanck, P. Schwabe, G. Seiler, D. Stehlé, CRYSTALS-Kyber (version 3.02) - Submission to Round 3 of the NIST PQC Project (2021).
[6]. Aikata, A. C. Mert, M. Imran, S. Pagliarini, S. S. Roy, KaLi: A crystal for post-quantum security using Kyber and Dilithium, IEEE Transactions on Circuits and Systems I: Regular Papers, 70(2) (2022) 747-758.
[7]. A. Dolmeta, M. Martina, G. Masera, Hardware architecture for CRYSTALS-Kyber post-quantum cryptographic SHA-3 primitives, Proc. 18th Conf. Ph.D. Research in Microelectronics and Electronics (PRIME), Valencia, Spain (2023) 209-212.
[8]. T. Kamucheka, A. Nelson, D. Andrews, M. Huang, A Masked Pure-Hardware Implementation of Kyber Cryptographic Algorithm, Proc. Int. Conf. Field-Programmable Technology (ICFPT) (2022).
[9]. P. Karl, J. Schupp, T. Fritzmann, G. Sigl, Post-Quantum Signatures on RISC-V with Hardware Acceleration, ACM Transactions on Embedded Computing Systems, 23(2) (2024) 30.
[10]. M. Sundal, R. Chaves, Efficient FPGA implementation of the SHA-3 hash function, Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (2017) 86-91. https://doi.org/10.1109/ISVLSI.2017.24
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[12]. A. Abdulsamad, S. R. Répáš, Design of an Energy-Efficient SHA-3 Accelerator on Artix-7 FPGA for Secure Network Applications, Computers, 15(1) (2026) 3. https://doi.org/10.3390/computers15010003
[13]. A. Sideris, T. Sanida, M. Dasygenis, High throughput implementation of the Keccak hash function using the NIOS-II processor, Technologies, 8(1) (2020) 15. https://doi.org/10.3390/technologies8010015
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[15]. A. Sideris, T. Sanida, M. Dasygenis, A Novel Hardware Architecture for Enhancing the Keccak Hash Function in FPGA Devices, Information, 14(9) (2023) 475. https://doi.org/10.3390/info14090475
[16]. A. Sideris, T. Sanida, M. Dasygenis, Hardware acceleration design of the SHA-3 for high throughput and low area on FPGA, Journal of Cryptographic Engineering, 14 (2024) 193-205.
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[18]. A. E. Putra, O. Natan, J. E. Istiyanto, Optimizing FPGA Resource Allocation for SHA-3 Using DSP48 and Pipelining Techniques, IIUM Engineering Journal, 26(1) (2025) 240-253. https://doaj.org/article/b9cca29bd44441cdb2ebf90f7b146ff6
[19]. A. Kermiche, M. Saoudi, A. Drouiche, High throughput pipelined implementation of SHA3 hash algorithm on FPGA, Journal of Cryptographic Engineering, 15(2) (2025) 15. https://doi.org/10.1007/s13389-025-00379-3
[20]. Lục Như Quỳnh et al., Triển khai thuật toán băm SHA-3 dựa trên kiến trúc RISC-V sử dụng phần cứng Arty A7-35T, Hội thảo khoa học “Công nghệ mới và ứng dụng trong lĩnh vực Điện - Điện tử - Tự động hóa”, Trường Đại học Giao thông vận tải (2026).
[21]. A. Akın, A. Aysu, O. C. Ulusel, E. Savaş, Efficient hardware implementations of high throughput SHA-3 candidates keccak, luffa and blue midnight wish for single- and multi-message hashing, Proc. 3rd Int. Conf. Security of Information and Networks (SIN) (2010) 168-177.
[22]. G. S. Athanasiou, G.-P. Makkas, G. Theodoridis, High throughput pipelined FPGA implementation of the new SHA-3 cryptographic hash algorithm, Proc. 6th Int. Symp. Communications, Control and Signal Processing (ISCCSP) (2014) 538-541.
[23]. C. Ewert, A. Sharma Poudel, M. Ayache, A. Neskovic, R. Buchty, M. Berekovic, S. Berndt, S. Mulhem, Lightweight Unified SHA-3/SHAKE Architecture with a Fault-Resilient State, arXiv:2512.03616 (2025).
[24]. J. Zhang, Y. Yan, J. Huang, Ç. K. Koç, Optimized Software Implementation of Keccak, Kyber, and Dilithium on RV{32,64}IM{B}{V}, IACR Transactions on Cryptographic Hardware and Embedded Systems, 2025(1) (2025) 632-655. https://doi.org/10.46586/tches.v2025.i1.632-655
[25]. D. Shin, Y. Kim, A. Khalid, M. O’Neill, S. C. Seo, Optimized Implementations of Keccak, Kyber, and Dilithium on the MSP430 Microcontroller, IACR Transactions on Cryptographic Hardware and Embedded Systems, 2026(2) (2026) 409-440. https://doi.org/10.46586/tches.v2026.i2.409-440
[26]. Đàm Đức Trung, Đặng Tuấn Anh, Thực thi thuật toán băm BLAKE3 trên bo mạch phát triển Raspberry Pi, Tạp chí Khoa học Giao thông vận tải, 76(5) (2025) 701-712. https://doi.org/10.47869/tcsj.76.5.5
[27]. V. A. Chhabria, W. Jiang, A. B. Kahng, S. S. Sapatnekar, From Global Route to Detailed Route: ML for Fast and Accurate Wire Parasitics and Timing Prediction, Proc. ACM/IEEE Workshop on Machine Learning for CAD (MLCAD) (2022). https://doi.org/10.1145/3551901.3556475
[28]. V. A. Chhabria, W. Jiang, A. B. Kahng, S. S. Sapatnekar, A Machine Learning Approach to Improving Timing Consistency between Global Route and Detailed Route, ACM Transactions on Design Automation of Electronic Systems, 29(1) (2023) 18. https://doi.org/10.1145/3626959
[29]. H. Jiang, Y. Guo, S. Guo, H. Liu, X. Li, N. Wang, Z. Di, Critical Path Aware Timing-Driven Global Placement for Large-Scale Heterogeneous FPGAs, arXiv:2512.00038 (2025).
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[31]. J. E. Stine, I. Castellanos, M. Wood, J. Henson, F. Love, W. R. Davis, P. D. Franzon, M. Bucher, S. Basavarajaiah, J. Oh, R. Jenkal, FreePDK: An Open-Source Variation-Aware Design Kit, Proc. IEEE Int. Conf. Microelectronic Systems Education (MSE) (2007) 173-174. https://doi.org/10.1109/MSE.2007.44
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[33]. C. H. M. Oliveira, M. T. Moreira, R. A. Guazzelli, N. L. V. Calazans, ASCEnD-FreePDK45: An open source standard cell library for asynchronous design, Proc. IEEE Int. Conf. Electronics, Circuits and Systems (ICECS) (2016) 652-655. https://doi.org/10.1109/ICECS.2016.7841286
[34]. M. L. L. Sartori, M. T. Moreira, N. L. V. Calazans, ASCEnD-FreePDK45: a free standard cell library for SDDS-NCL circuits (GitHub repository).
[35]. C. Torng, freepdk-45nm: ASIC design kit for FreePDK45 + Nangate for use with mflowgen (GitHub repository).
[36]. R. Thapa, S. Ataei, J. E. Stine, WIP: Open-source standard cell characterization process flow on 45 nm (FreePDK45), 0.18 µm, 0.25 µm, 0.35 µm and 0.5 µm, Proc. IEEE Int. Conf. Microelectronic Systems Education (MSE) (2017) 5-6. https://doi.org/10.1109/MSE.2017.7945072
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02/11/2026
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Nguyen Thanh, N., Nguyen Dac, K., Doan Duc, D., Tran Trong, H., Nguyen Anh, T., & Chu Thi Ngoc, Q. (1794675600). Timing bottleneck characterization in an iterative Keccak-f[1600]/SHA3-256 core: An FPGA/ASIC study. Tạp Chí Khoa Học Giao Thông Vận Tải, 77(9), 1138-1154. https://doi.org/10.47869/tcsj.77.9.2
