(1)
Nguyen Thanh, N.; Nguyen Dac, K.; Doan Duc, D.; Tran Trong, H.; Nguyen Anh, T.; Chu Thi Ngoc, Q. Timing Bottleneck Characterization in an Iterative Keccak-F[1600]/SHA3-256 Core: An FPGA/ASIC Study. vn 1794675600, 77, 1138-1154.